Offset compensated comparators are often used in analog to digital converters (ADCs). This is especially true for multi-bit ADCs where the comparator offset needs to be tightly controlled. One possible scheme is to connect these comparators to the driving (previous stage) amplifier through series switches. These switches are opened periodically to isolate the comparators. During this time the comparator inputs are shorted and the offset cancellation phase takes place. If the pre-amplifier in the comparator is configured in unity gain feedback, the offset is stored in the series capacitors connected at the input of the pre-amplifier. This is called input offset correction.
A typical prior art offset compensated comparator is shown in FIG. 1. Offset compensated comparator 120 is connected to a driving (previous stage) amplifier 122 through series switches 124 and 125. Offset compensated comparator 120 includes switches 124-129; comparator preamplifier 130; capacitors 132 and 134; parasitic capacitances 136 and 138; latch 140; inputs VINP and VINM; reference voltages VREFP and VREFM; latched bit 142; and latch enable 144. The previous stage amplifier 122 includes switches 150-160; amplifier 162; and capacitors 164-167.
For the prior art scheme shown in FIG. 1, the voltage at the input of pre-amplifier 130 is given by:VPRE-INP−VPRE-INM=[CS/(CS+CP)][(VINP−VINM)−(VREFP−VREFM)]where VPRE-INP is the voltage at node N1; VPRE-INM is the voltage at node N2; CS is the capacitance of capacitors 132 and 134; and CP is the parasitic capacitances 136 and 138 at the input of preamplifier 130. The input to the latch 140 is the input of preamplifier 130 multiplied by the gain of preamplifier 130.
Assuming that the offset of preamplifier 130 is completely removed by this scheme, the overall offset of the comparator 120 is thenOFFSET=OFFSETLATCH/[GAINPRE-AMP(CS/(CS+CP))]where OFFSETLATCH is the offset of latch 140, and GAINPRE-AMP is the gain of preamplifier 130.
VREFP and VREFM often have different output impedances. VREFP might be generated from a reference voltage buffer circuit and VREFM might be connected directly to ground. The AC settling of these two signals (onto capacitors 132 and 134) will be substantially different, where VREFM would settle quickly to ground and VREFP would settle more slowly to the positively generated reference.